AMD recently announced that the company is shedding its manufacturing operation, transferring its manufacturing assets to a new company. This will allow AMD to focus on design and engineering.
By late 2008, the company will have begun shipping its first set of 45nm quad-core CPUs based on the Phenom architecture. Code-named Shanghai, the new CPU will offer 6MB of L3 cache (up from 2MB) and HyperTransport 3 support. However, Shanghai will still have an embedded DDR2 memory controller, meaning that it will trail Intel in overall memory bandwidth.
Beyond this year, the company is prepping a 6-core CPU dubbed Istanbul, which is slated for a late 2009 launch. It's unlikely that there will be substantial changes to the architecture. The next new architecture for AMD is Magny Cours, which will have up to 12 cores and finally incorporate a DDR3 memory controller. A 6-core version, code-named Sao Paulo, will arrive on the scene about the same time, in early 2010.
Intel, on the other hand, likes to brag about its "tick-tock" development cycle. The phrase refers to the way Intel designs and transitions new architectures. When Intel develops a manufacturing process—such as its current 45nm technology—it brings an existing architecture to the new process. So Penryn, Intel's first 45nm CPU, was an evolutionary improvement over the original Core 2. That's the "tick." The "tock" is when Intel designs and builds a new CPU architecture on the current manufacturing process. Hence all the Nehalem variants will be built using the existing 45nm process.
In 2009, Intel will start to bring up its next-generation 32nm process, enabling it to pack even more transistors onto the same die size or shrink the CPU considerably. The 32nm process should also reduce power consumption and, in theory, enable higher clock speeds. The first processor built on 32nm will be Westmere and will be based on Nehalem.
Westmere may incorporate up to six cores on a single die. Intel has also announced that six new instructions designed to accelerate AES encryption/decryption algorithms will be part of the instruction set.
The true next generation for Intel isn't likely to hit the street until later in 2009 and will also be built on 32nm. That CPU is code-named Sandy Bridge. There's not a lot known about Sandy Bridge yet, but Intel is planning on integrating Advanced Vector Extensions, a new set of extensions to SSE that may considerably enhance the CPU's floating-point performance
